Schematics of delabs - Sample and Hold with Standby

Sample and Hold with Standby

A, B, and C are the Digital Control for x, y and z input and output pairs.The voltage at Vinx is stored in C1 when A goes high, when A is low the voltage stored in C1 is read by buffer U2A.

the stby or standby input should be low when sample and hold is operating.
if stby is taken high then C1 Cap is isolated and leakage is minimum.
The supply of +/- 7.5V is chosen as OFF resistance of 4053 is high at this supply.

Sample and Hold with Standby

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